A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy. 数字加法器需要更多的电路、因而需要更大的功率才能工作,但它不需要这么高的准确性。
Addend and the summand input, and digital and carry the output device is a half adder. 加法器是产生数的和的装置。加数和被加数为输入,和数与进位为输出的装置为半加器。
Add operation is one of the most fundamental operations in digital signal processing. The research on high-speed adder implement in programmable device should be recognized as all kinds of programmable device applied to the area of digital signal processing. 加法运算是数字信号处理最基本的运算,随着各种可编程逻辑器件在数字信号处理领域越来越多的应用,高速加法器在可编程器件上的研究应该得到人们的重视。
Development of a High Speed Digital Complex Multiply-adder 一种高速数字复数乘加器的研制
A new pulse stream digital/ analogue based synapse multiplier/ adder can be realized. The synapse weight values don't need learning, and it can also lessen the complexity of circuit. 实现了一种脉冲流数字模拟混合突触乘法/加法器电路,而且该神经网络电路的突触权值不需要学习调整,降低了电路的复杂性。
A new PRNs digital full adder algorithm and its implementation scheme 一种新的PRNS数母全加器算法及其实现方案
Design and test of a high speed PRNs digital full adder 高速PRNS数母全加器的设计及测试原则
A single-level perceptron network and field effect transistor circuit were used to make a digital/ analogue-based synapse multiplier/ adder. 利用单层感知器网络、场效应管电路实现了一种新的数字模拟混合突触乘法/加法器电路。
This article introduce the principle of Digital Signal Processor, specially refer to basic concept and design technique, include: instruction set, pipeline, memory organization, hardware interface, adder, multiplier, clock strategy, test technique. 阐述了数字信号处理器的原理,重点介绍了设计数字信号处理器芯片的简单概念及设计方法,包括指令集、流水线、存储器组织、硬件接口、加法器、乘法器、时钟方案、测试接口等等。